The present invention relates to modifying the geometry of a sidewall of a deep trench storage capacitor, and more particularly to the preparation of a notched collar isolation for suppression of vertical parasitic current leakage in a metal oxide semiconductor field effect transistor (MOSFET).
A MOSFET is used in forming dynamic random access memory (DRAM). A DRAM circuit will usually include an array of memory cells interconnected by rows and columns, which are known as wordlines and bitlines, respectively. Reading data from or writing data to memory cells is achieved by activating selected wordlines and bitlines. Typically, a DRAM memory cell comprises a MOSFET connected to a capacitor. The capacitor includes gate and diffusion regions which are referred to as either drain or source regions, depending on the operation of the transistor.
There are different types of MOSFETs. A planar MOSFET is a transistor where a surface of the channel region of the transistor is generally parallel to the primary surface of the substrate. A vertical MOSFET is a transistor where a surface of the channel region of the transistor is generally perpendicular to the primary surface of the substrate. A trench MOSFET is a transistor where a surface of the channel region of the transistor is not parallel to the primary surface of the substrate and the channel region lies within the substrate. For a trench MOSFET, the surface of the channel region is usually perpendicular to the primary surface, although this is not required.
Specifically, trench capacitors are frequently used with DRAM cells. A trench capacitor is a three-dimensional structure formed into a silicon substrate. This is normally formed by etching trenches of various dimensions into the silicon substrate. Trenches commonly have N+ doped poly as one plate of the capacitor (a storage node). The other plate of the capacitor is formed usually by diffusing N+ dopants out from a dopant source into a portion of the substrate surrounding the lower part of the trench. Between these two plates, a dielectric layer is placed which thereby forms the capacitor.
To prevent carriers from traveling through the substrate between the adjacent devices, e.g. capacitors, device isolation regions are formed between adjacent semiconductor devices. Generally, device isolation regions take the form of thick field oxide regions extending below the surface of the semiconductor substrate. The most common early technique for forming a field oxide region is the local oxidation of silicon (xe2x80x9cLOCOSxe2x80x9d) technique. LOCOS field oxidation regions are formed by first depositing a layer of silicon nitride (xe2x80x9cnitridexe2x80x9d) on the substrate surface and then selectively etching a portion of the silicon nitride layer to form a mask exposing the substrate where the field oxidation will be formed. The masked substrate is placed in an oxidation environment and a thick silicon oxide layer is grown at the regions exposed by the mask, forming an oxide layer extending above and below the surface of the substrate. An alternative to LOCOS field oxidation is the use of shallow trench isolation (xe2x80x9cSTIxe2x80x9d). In STI, a sharply defined trench is formed in the semiconductor substrate by, for example, anisotropic etching. The trench is filled with oxide back to the surface of the substrate to provide a device isolation region. Trench isolation regions formed by STI have the advantages of providing device isolation across their entire lateral extent and of providing a more planar structure. Using improved isolation, continued reductions in size are possible.
With continued scaling of minimum feature size in the DRAM array, reduction of the lateral dimensions (the openings) of the deep trench (DT) storage capacitor results. Further, the shift from currently practiced cell area of 8F2 (F is the minimum linewidth of the feature size that can be patterned with lithography) for planar MOSFET cells to a cell area of 7F2 and 6F2 for planar and vertical MOSFET cells. This is driving the design opening of the trench capacitor from a 1:2 towards a 1:1 width to length ratio. A reduction in the size opening of the storage trench makes filling the deep trench with conductive material more difficult. Further, the difficulty in filling the DT is further compounded since the collar isolation oxide thickness requirement does not scale significantly from generation to generation.
To reduce parasitic leakage along an upper portion of the trench, an oxide collar is provided. Another way to reduce parasitic leakage is to increase the amount of dopant in the well of the transistor. However, increasing the amount of dopant will typically increase the electric fields in the depletion regions. This results in a sharp increase in junction leakage.
Suppression of the vertical parasitic MOSFET leakage required for long data retention time, between the storage node diffusion (buried-strap out-diffusion) and the N+ buried-plate, along the trench sidewall, is constrained by the minimum thickness of the collar isolation oxide and/or the minium doping concentration in the deep portion of the array P-well. If desired to alleviate the DT fill difficulty by thinning the collar isolation oxide, the doping concentration in the array P-well is generally increased to compensate. However by increasing the P-well concentration, data retention time is degraded. Also, having a very small DT opening within the collar isolation region adds to the series resistance of the trench capacitor. An increased resistance limits the amount of charge that can be stored which thereby degrades the yield of a capacitor.
There is a need in the art for an improved method of preparing a notched collar isolation for suppression of vertical parasitic MOSFET and the product thereof.
The present invention is a deep trench storage capacitor having a modified sidewall geometry within the collar isolation region. The deep trench capacitor, comprises a silicon substrate; a trench within the silicon substrate, the trench having one or more walls; first and second N+ plates positioned within the silicon substrate at a bottom portion of the trench; a P-well region within the silicon substrate positioned above the first and the second N+ plates; a notch formed within the one or more walls of the trench; a N+ strap disposed adjacent to the trench; an STI positioned adjacent to the trench and on a top portion of the silicon substrate; a node dielectric on the sidewalls of a lower portion of the trench; a first oxide coating disposed on the walls of the trench; a polycrystalline silicon disposed within the trench; and a second oxide coating disposed over the trench.
The present invention is also method of making a deep trench capacitor which comprises providing a silicon substrate; forming a notch within one or more walls of a trench within the silicon substrate; providing first and second N+ plates within the silicon substrate at a bottom portion of the trench, a P-well region within the silicon substrate positioned above the first and the second N+ plates, a N+ strap adjacent to the trench, an STI adjacent to the trench and on a top portion of the silicon substrate, a node dielectric on the sidewalls of a lower portion of the trench; a first oxide coating on the walls of the trench, a polycrystalline silicon within the trench, and a second oxide coating over the trench.
The above discussed and other features and advantages of the present invention will be appreciated and understood by those skilled in the art from the following detailed description and drawings.